Instructions used in various instructions set architectures (ISAs) in various processors may include operations that involve either or both generating a mask value that is to be logically combined with another value to produce a resultant value. A mask value may be stored in a memory location, such as a register (“vector mask”), and contain a number of bits that are to be used in a Boolean logic operation (e.g., “AND” operation) with a corresponding number of bits of another value. FIG. 1, for example, illustrates a vector mask 101 whose bits are to be logically combined via a Boolean AND operation with the bits of another value stored in another register 105 to yield a resultant value stored in a resultant register 110.
In some ISAs, instructions may be designated as being instructions that use a mask value to generate a result. For example, if an instruction is designated as being executed “under mask”, a data value used by or produced by the instruction may be stored in a processor registers, such as a “vector register”. In turn, operations performed on data stored in the vector register element may check the corresponding bit in the vector mask, which may be stored in a “vector mask register”. If a corresponding bit is set at a certain value, the operation may be carried out without regard to the vector mask. On the other hand, if the bit is set to another value, the operation may be ignored, for example, and no exceptions and/or results are produced for that operation. The number of bits within the vector mask and the meaning of each bit in the vector mask may vary according to the processor architecture in which it's implemented.
Vector masks can be initialized or “set” through various techniques, including using an operation or sequence of operations, such as operations decoded from an instruction (“uop”), to set the vector mask from another registers, such as a scalar register. Alternatively, some prior art techniques set the vector mask implicitly through the performance of other operations, such as a “compare” operation. In one prior art technique, a vector mask is set using a first operation to compare (e.g., “veq” operation) a mask value with another value, such as a vector of “zero” values, to produce a value that can then be stored into the vector mask by performing a second operation to set the vector mask (e.g., “setvm” operation).
Some prior art techniques have used an operation or operations to generate a vector mask value and another operation or operations to store the vector mask in a storage location, such as a register, from which the vector mask may be applied to various instructions that use it.
One shortcoming of prior art techniques, such as the one described above, is that two or more operations must be performed to ultimately set the vector mask before it can be used, which requires extra processing cycles, thereby impacting processing performance.